Reducing leakage current in memory cells
US6628551B2 · kind B2 · utility
70Cited by
8References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 14, 2001 |
| Grant date | Sep 30, 2003 |
| Priority date | — |
| Expiry date | Aug 7, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/05
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell having first and second access transistors coupled to a storage transistor is disclosed. The access transistors are high gate threshold voltage transistors to reduce leakage current in the memory cell. The gate threshold voltage of the access transistors are, for example, 0.1 to 0.4V higher than typical transistors. Reducing leakage current advantageously improves the retention time of the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.