Method and apparatus for low power memory bit line precharge
US6629194B2 · kind B2 · utility
5Cited by
10References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 31, 2001 |
| Grant date | Sep 30, 2003 |
| Priority date | — |
| Expiry date | Jul 16, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2281
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes a plurality of banks of memory elements. For a memory read access operation, bank enable logic coupled to each of the plurality of banks is responsive to an address of a memory element to be read to selectively deactivate a first precharge clock signal to be received by a first one of the banks that includes the memory element to be read. The bank enable logic is further responsive to the address to selectively maintain in an active state a second precharge clock signal to be received by a second one of the banks that does not include the memory element to be read.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.