Condition code register architecture for supporting multiple execution units
US6629235B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2000 |
| Grant date | Sep 30, 2003 |
| Priority date | — |
| Expiry date | May 5, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A condition code register architecture for supporting multiple execution units is disclosed. A master execution unit is coupled a master condition code register such that condition codes generated by the master execution unit are stored in the master condition code register. A non-master execution unit is coupled to a shadow condition code register such that condition codes generated by the non-master execution unit are stored in the shadow condition code register. A tag unit coupled to the master execution unit and the non-master execution unit such that an entry within the master condition code register can be read only when a corresponding entry within the tag unit is referenced to the master execution unit or the master condition code register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.