Inventor · Austin, TX, US

Brian Flachs

50Patents
8h-index
60Co-inventors
77Inventor score

Filing activity: Dec 10, 1999 → Dec 26, 2017

Most-cited inventions

PatentTitleAreaCited byStatus
US8520740B2 Arithmetic decoding acceleration Electricity 50 Active
US6598153B1 Processor and method that accelerate evaluation of pairs of condition-setting and branch instructions Physics 36 Expired
US7447602B1 System and method for sorting processors based on thermal design point Physics 16 Active
US8522225B2 Rewriting branch instructions using branch stubs Physics 15 Active
US8381006B2 Reducing power requirements of a multiple core processor Emerging Cross-Sectional Technologies 15 Active
US7533238B2 Method for limiting the size of a local storage of a processor Physics 13 Active
US8516230B2 SPE software instruction cache Physics 10 Active
US7197655B2 Lowered PU power usage method and apparatus Physics 8 Expired
US8631225B2 Dynamically rewriting branch instructions to directly target an instruction cache location Physics 7 Active
US6600959B1 Method and apparatus for implementing microprocessor control logic using dynamic programmable logic arrays Electricity 6 Expired
US7486096B2 Method and apparatus for testing to determine minimum operating voltages in electronic devices Physics 6 Active
US8713548B2 Rewriting branch instructions using branch stubs Physics 6 Active
US8782381B2 Dynamically rewriting branch instructions in response to cache line eviction Physics 6 Active
US8627051B2 Dynamically rewriting branch instructions to directly target an instruction cache location Physics 5 Active
US6629235B1 Condition code register architecture for supporting multiple execution units Physics 5 Expired
US7610531B2 Modifying a test pattern to control power supply noise Physics 4 Active
US8726252B2 Management of conditional branches within a data parallel system Physics 4 Active
US7617338B2 Memory with combined line and word access Physics 4 Active
US10169013B2 Arranging binary code based on call graph partitioning Physics 4 Active
US7203608B1 Impedane measurement of chip, package, and board power supply system using pseudo impulse response Physics 4 Active
US9459851B2 Arranging binary code based on call graph partitioning Physics 3 Active
US8359435B2 Optimization of software instruction cache by line re-ordering Physics 3 Active
US8683185B2 Ceasing parallel processing of first set of loops upon selectable number of monitored terminations and processing second set Physics 2 Active
US8627043B2 Data parallel function call for determining if called routine is data parallel Physics 2 Active
US7170316B2 Programmable logic array latch Electricity 2 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.