Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device
US6630375B2 · kind B2 · utility
6Cited by
23References
4Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 5, 2001 |
| Grant date | Oct 7, 2003 |
| Priority date | — |
| Expiry date | Mar 21, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS·FETs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.