Method for forming capacitor of semiconductor memory device using electroplating method
US6630387B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 19, 2001 |
| Grant date | Oct 7, 2003 |
| Priority date | — |
| Expiry date | Mar 19, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a capacitor of a semiconductor memory device is provided. In the capacitor formation, a insulating layer is deposited over a semiconductor substrate, and patterned into a insulating pattern with a hole that exposes the semiconductor substrate. Next, a seed layer for use in forming a lower electrode is formed over the surface of the exposed semiconductor substrate, the inner walls of the hole, and the insulating pattern, and a plating mask layer is selectively formed on the seed layer deposited on the insulating pattern, and on a portion of the seed layer from the upper edges of the insulating pattern deposited along the sidewalls of the hole to a predetermined depth, such that the seed layer formed in the hole is exposed. The plating mask layer is formed by a physical vapor deposition (PVD) or a plasma chemical vapor deposition (CVD) method. Next, a conductive layer is formed on the exposed seed layer by electroplating, and then etched to form a conductive pattern and a seed pattern separated by a unit cell. The insulating pattern formed on the outer walls of the hole is removed to complete a lower electrode of the capacitor formed of the conductive pattern. The…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.