Method for fabricating flash memory device
US6630392B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2001 |
| Grant date | Oct 7, 2003 |
| Priority date | — |
| Expiry date | Dec 31, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/48
Abstract
A method for fabricating a flash memory device begins with forming in sequence a tunnel oxide layer, a floating gate, an oxide-nitride-oxide (ONO) layer, a control gate, and a hard mask nitride layer on a silicon substrate. The hard mask nitride layer, the control gate, the ONO layer, and the floating gate are then patterned in sequence. Next, a sealing nitride layer is formed on a lateral side of the patterned structure. Also, in order to form a spacer, a first insulating layer is deposited on an entire resultant structure and then selectively patterned. Thereafter, second, third and fourth insulating layers are formed in sequence on the entire resultant structure including the spacer, and a photo resist pattern is then formed on the fourth insulating layer to define a metal contact area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.