Twin MONOS array metal bit organization and single cell operation
US6631088B2 · kind B2 · utility
12Cited by
6References
35Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2002 |
| Grant date | Oct 7, 2003 |
| Priority date | — |
| Expiry date | Jul 8, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In the present invention a twin MONOS metal bit line array is read and programmed using a three dimensional programming method with X, Y and Z dimensions. The word line address is the X address. The control gate line address is a function of the X and Z addresses, and the bit line address is a function of the Y and Z addresses. Because the bit lines and the control gate lines of the memory array are orthogonal a single cell can be erased with an adjacent memory, having the same selected bit and control gate lines, being inhibited from erase by application of the proper voltages to unselected word, control gate and bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.