Bit line decoding scheme and circuit for dual bit memory array
US6631089B1 · kind B1 · utility
8Cited by
5References
35Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2002 |
| Grant date | Oct 7, 2003 |
| Priority date | — |
| Expiry date | Jul 8, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In the present invention a bit line decoder circuit a method of selecting bit lines for read and program operations is described for a twin MONOS memory cell array. A block of twin MONOS memory cells is partitioned into sub-blocks wherein decode signals select bit lines to be read and programmed, and select adjacent bit lines to provide bias for the read and program operations. The bit lines are partitioned into even and odd addresses within each sub-block, and an even and odd address sub-block selector connects the selected bit line along with adjacent bit lines to sense amplifiers and memory chip I/O.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.