Low power precharge scheme for memory bit lines
US6631093B2 · kind B2 · utility
8Cited by
8References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2001 |
| Grant date | Oct 7, 2003 |
| Priority date | — |
| Expiry date | Jun 29, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A low power memory bit line precharge scheme. A memory bit line is coupled to a first read precharge device. A second write precharge device is also coupled to the memory bit line and is to be enabled only in response to a memory write operation. The first read and second write precharge devices are sized such that their combined drive strength is sufficient to precharge the first memory bit line during a precharge period following a write operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.