Method of analyzing integrated circuit power distribution in chips containing voltage islands
US6631502B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2002 |
| Grant date | Oct 7, 2003 |
| Priority date | — |
| Expiry date | Jan 16, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of analyzing the power distribution in a chip containing one or more voltage islands, each voltage island having a power distribution network connected to a chip-level power distribution network by one or more voltage translation interface circuits. The method comprising: analyzing the voltage-island power distribution networks independently of the chip-level power distribution network to obtain voltage translation interface circuit currents; using the voltage translation interface circuit currents as input to a model of the chip-level power distribution network to obtain voltage translation interface circuit input voltages; and calculating voltage translation interface circuit output voltages based on the voltage translation interface circuit input voltages, the voltage translation interface circuit currents, and current-voltage characteristics of the voltage translation interface circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.