Disposable spacer technology for reduced cost CMOS processing
US6632718B1 · kind B1 · utility
46Cited by
10References
14Claims
0Family size
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Key dates
| Filing date | Jun 24, 1999 |
| Grant date | Oct 14, 2003 |
| Priority date | — |
| Expiry date | Jun 24, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0184
Abstract
A method of fabricating a CMOS transistor using a silicon germanium disposable spacer (114) for the source/drain implant. After gate etch, silicon germanium disposable spacers (114) are formed. A NMOS resist pattern (116) is formed exposing the NMOS regions (120) and the n-type source/drain implant is performed. The disposable spacers (114) in the NMOS regions are removed and, with the NMOS resist mask (116) still in place, the LDD/MDD implant is performed. The process may then be repeated for the PMOS regions (122).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.