Method of manufacturing semiconductor devices having capacitors with electrode including hemispherical grains
US6632721B1 · kind B1 · utility
7Cited by
9References
20Claims
0Family size
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Key dates
| Filing date | Jun 23, 2000 |
| Grant date | Oct 14, 2003 |
| Priority date | — |
| Expiry date | Jun 23, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/315
Abstract
In a method of manufacturing a semiconductor integrated circuit device in which a lower electrode of a capacitor is composed of a polycrystalline silicon film having a surface area increased by surface roughening, an impurity is introduced into the polycrystalline silicon film by vapor phase diffusion in order to reduce the resistance of the lower electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.