Method for avoiding defects produced in the CMP process
US6632742B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2001 |
| Grant date | Oct 14, 2003 |
| Priority date | — |
| Expiry date | Apr 21, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7684
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for avoiding defects produced in The CMP process has the following steps: sequentially depositing a first dielectric layer and a second dielectric layer on a semiconductor substrate, wherein the wet-etching rate of the first dielectric layer is greater than the wet-etching rate of the second dielectric layer; forming a plurality of first holes on a plurality of the predetermined contact window areas respectively; wet etching the first dielectric layer in each of the first holes to form a plurality of second holes on the plurality of the predetermined contact window areas respectively; forming a conductive layer to fill each of the second holes; and performing the CMP process to level off the conductive layer and the second dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.