Programmable gate array based on configurable metal interconnect vias
US6633182B2 · kind B2 · utility
232Cited by
20References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2001 |
| Grant date | Oct 14, 2003 |
| Priority date | — |
| Expiry date | Sep 5, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is comprised of translating a bit stream defining the state of switches of an FPGA into a set of via geometries, or generating the set of via geometries directly from a physical design system. The via geometries are used to produce at least one via mask. The via mask is then used in a manufacturing process to customize an array of fixed and/or programmable logic blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.