Pixel clock PLL frequency and phase optimization in sampling of video signals for high quality image display
US6633288B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 1999 |
| Grant date | Oct 14, 2003 |
| Priority date | — |
| Expiry date | Sep 15, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/008
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Pixel clock frequency and optimum sampling phase adjustment is an important requirement in Flat panel display monitors (FPDM) with an analog video interface. This invention proposes a new and more advanced method for frequency and optimum sampling phase determination. It is based on analyzing the content of the image to arrive at an optimum value of phase and frequency by directly optimizing image quality. The method differs from existing methods on two counts. First, no assumptions are needed about the precise value of expected frequency. Second, instead of following a two step approach of first determining frequency and then phase, this invention makes possible a single pass phase-frequency optimization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.