Sandeep Agarwal
30Patents
8h-index
46Co-inventors
75Inventor score
Filing activity: Sep 15, 1999 → Sep 29, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7205798B1 | Phase error correction circuit for a high speed frequency synthesizer | Electricity | 60 | Expired |
| US8108715B1 | Systems and methods for resolving split-brain scenarios in computer clusters | Physics | 39 | Active |
| US9454444B1 | Using location tracking of cluster nodes to avoid single points of failure | Physics | 27 | Active |
| US7944192B2 | Hysteretic power-supply controller with adjustable switching frequency, and related power supply, system, and method | Electricity | 17 | Active |
| US9043467B2 | Adaptive chunked and content-aware pacing of multi-media delivery over HTTP transport and network controlled bit rate selection | Electricity | 14 | Active |
| US6633288B2 | Pixel clock PLL frequency and phase optimization in sampling of video signals for high quality image display | Physics | 11 | Expired |
| US10848098B2 | Smart energy storage system | Emerging Cross-Sectional Technologies | 10 | Active |
| US8489721B1 | Method and apparatus for providing high availabilty to service groups within a datacenter | Electricity | 8 | Active |
| US10120769B2 | Raid rebuild algorithm with low I/O impact | Physics | 4 | Active |
| US11658995B1 | Methods for dynamically mitigating network attacks and devices thereof | Electricity | 4 | Active |
| US7592846B2 | Method for using digital PLL in a voltage regulator | Electricity | 3 | Active |
| US6933937B2 | Pixel clock PLL frequency and phase optimization in sampling of video signals for high quality image display | Physics | 3 | Expired |
| US11560183B2 | Truck bedslide assembly | Performing Operations; Transporting | 3 | Active |
| US8159276B2 | Method for using digital PLL in a voltage regulator | Electricity | 3 | Active |
| US6735349B1 | Method and system for dual spatial or temporal scaling | Physics | 3 | Expired |
| US9811282B2 | Efficient rebuild of storage devices in a redundant array of independent disks (RAID) | Physics | 2 | Active |
| US9569342B2 | Test strategy for profile-guided code execution optimizers | Physics | 2 | Active |
| US10565108B2 | Write-back cache for storage controller using persistent system memory | Physics | 2 | Active |
| US9535619B2 | Enhanced reconstruction in an array of information storage devices by physical disk reduction without losing data | Physics | 2 | Active |
| US10521318B2 | Spanned RAID with nested parity | Physics | 2 | Active |
| US7498852B1 | Phase error correction circuit for a high speed frequency synthesizer | Electricity | 1 | Active |
| US10007432B2 | System and method for replacing storage devices | Physics | 1 | Active |
| US9652394B2 | System and method for managing a cache pool | Physics | 1 | Active |
| US12401685B2 | Methods for mitigating DDoS attack using hardware device and devices thereof | Electricity | 0 | Active |
| US9665292B2 | System and method for providing consistent metadata for RAID solutions | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.