Programmable refresh scheduler for embedded DRAMs
US6633952B2 · kind B2 · utility
9Cited by
5References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2001 |
| Grant date | Oct 14, 2003 |
| Priority date | — |
| Expiry date | Nov 22, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one aspect, the invention describes a mechanism for refreshing multiple memory words (rows) per refresh cycle, the number of simultaneously refreshed rows being programmable by a small number of inputs. In another aspect, the invention discloses a mechanism for refreshing all banks or a programmable number of banks simultaneously in a multi-bank memory. In yet another aspect, the present invention describes a mechanism for refreshing a programmable multiple memory rows and a programmable multiple banks simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.