System and method for testing an interface between two digital integrated circuits
US6634005B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2000 |
| Grant date | Oct 14, 2003 |
| Priority date | — |
| Expiry date | May 1, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/267
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method for testing at least one interface of a digital integrated circuit while at least one other interface of the digital integrated circuit operates in a normal mode is disclosed. Each interface includes at least one boundary scan cell such that each boundary scan cell is electrically coupled to a pin of the digital integrated circuit. The method includes selectively categorizing at least one interface into a first category. At least one other interface is selectively categorized into a second category. A first mode signal is provided to the interfaces categorized into the test mode category such that the interfaces categorized into the test mode category operate in a test mode. A second mode signal is provided to the interfaces categorized into the normal operation mode category such that the interfaces categorized into the normal operation mode category operate in a normal operation mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.