Delay/load estimation for use in integrated circuit design
US6634014B1 · kind B1 · utility
9Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2000 |
| Grant date | Oct 14, 2003 |
| Priority date | — |
| Expiry date | May 24, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Delay and/or load estimation is performed prior to physical layout in an integrated circuit (IC) design process. Initially, a description of the IC design is obtained, the description being in a hardware description language (HDL). Floor planning is then performed based on the HDL description, and buffers are inserted into the IC design based on such floor planning. Finally, delays and/or loads are estimated in the IC design while taking into account the effect of the buffers. The buffers are inserted in the foregoing processing based on anticipated processing later in the IC design process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.