Cyclic thermal anneal for dislocation reduction
US6635110B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2000 |
| Grant date | Oct 21, 2003 |
| Priority date | — |
| Expiry date | Jun 23, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02255
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides processes for producing a very low dislocation density in heterogeneous epitaxial layers with a wide range of thicknesses, including a thickness compatible with conventional silicon CMOS processing. In a process for reducing dislocation density in a semiconductor material formed as an epitaxial layer upon a dissimilar substrate material, the epitaxial layer and the substrate are heated at a heating temperature that is less than about a characteristic temperature of melting of the epitaxial layer but greater than about a temperature above which the epitaxial layer is characterized by plasticity, for a first time duration. Then the epitaxial layer and the substrate are cooled at a cooling temperature that is lower than the about the heating temperature, for a second time duration. These heating and cooling steps are carried out a selected number of cycles to reduce the dislocation density of the epitaxial layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.