Wafer-level MEMS packaging
US6635509B1 · kind B1 · utility
205Cited by
10References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 12, 2002 |
| Grant date | Oct 21, 2003 |
| Priority date | — |
| Expiry date | Apr 12, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A competitive, simple, single-substrate wafer-level packaging technique capable of creating a vacuum-sealed protective cavity around moving or other particular components of a MEMS is described. The technique uses common semiconductor materials, processing steps and equipment to provide a stable vacuum environment of, for example less than 1 Pa, in a sealed cavity. The environment protects components of the MEMS against micro-contamination from particles and slurry of a waver dicing process and against fluctuations of atmospheric condition to ensure long term reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.