Method of fabricating flash memory
US6635533B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2003 |
| Grant date | Oct 21, 2003 |
| Priority date | — |
| Expiry date | Mar 27, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6892
Abstract
A method of fabricating a flash memory is provided. A pad layer and a mask layer are formed over the substrate, and then the mask layer is patterned for forming an opening therein. The pad layer exposed by the opening is removed. After a tunneling dielectric layer is formed on the bottom of the opening, a floating gate is formed on the sidewall of the opening. The top of the floating gate is lower than a surface of the mask layer. A source region is formed in the substrate. Thereafter, an inter-gate dielectric layer is formed in the opening and a control gate is filled in the opening. The mask layer is removed and then a gate dielectric layer is formed on the substrate and a spacer is formed on the sidewall of the floating gate and the control gate. A select gate is formed on the sidewall of the spacer. A drain region is formed in the substrate on one side of the select gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.