Method for manufacturing semiconductor memory device
US6635536B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2001 |
| Grant date | Oct 21, 2003 |
| Priority date | — |
| Expiry date | Apr 18, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/05
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor memory device is disclosed. A spacer of a material having a high etching selection ratio with respect to an interdielectric layer is formed on a sidewall of a gate electrode. A refractory metal silicide layer is formed on an upper surface of the gate electrode and on an upper surface of a substrate on which source and drain regions are formed, thereby providing a contact hole self-aligned between the gate electrodes. Also, an ion implantation process is performed on the entire active region after the contact hole is filled with metal such as tungsten, and an impurity region is formed only on a lower portion of the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.