Semiconductor integrated circuit device and method for manufacturing the same
US6635918B1 · kind B1 · utility
10Cited by
13References
21Claims
0Family size
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Key dates
| Filing date | Nov 17, 2000 |
| Grant date | Oct 21, 2003 |
| Priority date | — |
| Expiry date | Jan 26, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/915
Abstract
The sheet resistance of a gate electrode 8A (a word line) of memory cell selection MISFET Q a DRAM and a sheet resistance of bit lines BL1, BL2 are, respectively, 2 &OHgr;/□ or below. Interconnections of a peripheral circuit are formed during the step of forming the gate electrode 8A (the word line WL) or the bit lines BL1, BL2 by which the number of the steps of manufacturing the DRAM can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.