Component level, CPU-testable, multi-chip package using grid arrays
US6636825B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 1999 |
| Grant date | Oct 21, 2003 |
| Priority date | — |
| Expiry date | Jul 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/48
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for performing electrical acceptance tests on a sub-system including a test substrate, a microprocessor and one or more associated computer components, such as SRAM, DRAM and ROM. A pin grid array, ball grid array, line grid array or equivalent test connector system is provided that allows direct addressing of selected circuits of the microprocessor and of each associated component. The microprocessor plus substrate are first tested together. If this test is successful, the associated components are then added, preferably one at a time, and the new sub-system is tested. If a particular sub-system fails a test, the cause(s) of failure can be isolated and removed, where possible, and the modified sub-system can be retested.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.