Method and apparatus for processor bypass path to system memory
US6636939B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 29, 2000 |
| Grant date | Oct 21, 2003 |
| Priority date | — |
| Expiry date | Aug 20, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory interface unit is described having a first interface to receive a first request from a processor where the first request has an attribute. The memory interface unit also has a second interface to receive a second request from the processor where the second request does not have the attribute. The memory interface unit also has a third interface to read/write information from/to a system memory. A method is also described that involves forwarding a processor request along a first path to a memory interface unit if the request has one or more attributes; and forwarding the request along a second path to the memory interface unit if the processor request does not have the one or more attributes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.