Computer architecture for shared memory access
US6636950B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 1999 |
| Grant date | Oct 21, 2003 |
| Priority date | — |
| Expiry date | Apr 27, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer architecture that includes a hierarchical memory system and one or more processors. The processors execute memory access instructions whose semantics are defined in terms of the hierarchical structure of the memory system. That is, rather than attempting to maintain the illusion that the memory system is shared by all processors such that changes made by one processor are immediately visible to other processors, the memory access instructions explicitly address access to a processor-specific memory, and data transfer between the processor-specific memory and the shared memory system. Various alternative embodiments of the memory system are compatible with these instructions. These alternative embodiments do not change the semantic meaning of a computer program which uses the memory access instructions, but allow different approaches to how and when data is actually passed from one processor to another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.