Technique for gated lateral bipolar transistors
US6638807B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2001 |
| Grant date | Oct 28, 2003 |
| Priority date | — |
| Expiry date | Nov 27, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/645
Abstract
An improved structure and method for gated lateral bipolar transistors are provided. Embodiments of the present invention capitalize on opposing sidewalls and adjacent conductive sidewall members to conserve available surface space on the semiconductor chips. Additionally, the gate and body of the transistors are biased to modify the threshold voltage of the transistor (Vt). The conductive sidewall member configuration conserves surface space and achieves a higher density of surface structures per chip. The structures offer performance advantages from both metal-oxide semiconductor (MOS) and bipolar junction transistor (BJT) designs. The devices can be used in a variety of applications, digital and analog, wherever a more compact structure with low power consumption and fast response time is needed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.