Power MOS device with buried gate
US6638826B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2002 |
| Grant date | Oct 28, 2003 |
| Priority date | — |
| Expiry date | Jul 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/256
Abstract
An MOS power device a substrate comprises an upper layer having an upper surface and an underlying drain region, a well region of a first conductance type disposed in the upper layer over the drain region, and a plurality of spaced apart buried gates, each of which comprises a trench that extends from the upper surface of the upper layer through the well region into the drain region. Each trench comprises an insulating material lining its surface, a conductive material filling its lower portion to a selected level substantially below the upper surface of the upper layer, and an insulating material substantially filling the remainder of the trench. A plurality of highly doped source regions of a second conductance type are disposed in the upper layer adjacent the upper portion of each trench, each source region extending from the upper surface to a depth in the upper layer selected to provide overlap between the source regions and the conductive material in the trenches. A groove in each of the highly doped source regions extends through the source regions into the well region and terminates in a nadir. A highly doped body region of a first conductance type is disposed in the well r…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.