Semiconductor structure including a partially annealed layer and method of forming the same
US6638838B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2000 |
| Grant date | Oct 28, 2003 |
| Priority date | — |
| Expiry date | Oct 2, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0251
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. To further relieve strain in the accommodating buffer layer, at least a portion of the accommodating buffer layer is exposed to a laser anneal process to cause the accommodating buffer layer to become amorphous, providing a true compliant substrate for subsequent layer growth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.