Electropolishing metal layers on wafers having trenches or vias with dummy structures
US6638863B2 · kind B2 · utility
25Cited by
12References
82Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2002 |
| Grant date | Oct 28, 2003 |
| Priority date | — |
| Expiry date | Mar 27, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7684
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
In electropolishing a metal layer on a semiconductor wafer, a dielectric layer is formed on the semiconductor wafer. The dielectric layer is formed with a recessed area and a non-recessed area. A plurality of dummy structures are formed within the recessed areas where the dummy structures are inactive areas configured to increase the planarity of a metal layer subsequently formed on the dielectric layer. A metal layer is then formed to fill the recessed area and cover the non-recessed area and the plurality of dummy structures. The metal layer is then electropolished to expose the non-recessed area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.