Method and structure for surface state passivation to improve yield and reliability of integrated circuit structures
US6639264B1 · kind B1 · utility
11Cited by
13References
14Claims
0Family size
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Inventor
Key dates
| Filing date | Dec 11, 1998 |
| Grant date | Oct 28, 2003 |
| Priority date | — |
| Expiry date | Dec 11, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/05
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for passivating surface states in an integrated circuit structure having a gate conductor with a gate dielectric layer. The method comprises the step of fabricating a solid state source of fluorine in close proximity to the gate dielectric layer. In addition, an integrated circuit structure is provided. The structure comprises a substrate having a gate dielectric layer on the substrate and a gate conductor on the substrate above the gate dielectric layer. The gate conductor further comprises an edge and a solid state source of fluorine in close proximity to the gate dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.