Clock signal correction circuit and semiconductor device implementing the same
US6639441B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2002 |
| Grant date | Oct 28, 2003 |
| Priority date | — |
| Expiry date | Jan 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/159
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock signal correction circuit which corrects duty cycle distortions of a clock signal in a simple and accurate way. A frequency divider divides the frequency of a given input clock signal by a natural number n, thereby producing a divided clock signal. The phase of this divided clock signal is identified by a phase detector. By adding an appropriate delay to the divided clock signal according to the identified signal phase, a delay unit produces a delayed divided clock signal. A logical operator creates an output clock signal by performing a logical operation on the original divided clock signal and the delayed divided clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.