Memory buffer arrangement
US6639820B1 · kind B1 · utility
98Cited by
4References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2002 |
| Grant date | Oct 28, 2003 |
| Priority date | — |
| Expiry date | Jun 27, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory modules, memory systems, and computing devices are described which include memory buffer devices that buffer signals of memory devices. In some embodiments, the memory buffer devices are positioned to reduce the circuit board footprint of the memory buffer devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.