Method for reading flash memory with silicon-oxide/nitride/oxide-silicon (SONOS) structure
US6639836B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2002 |
| Grant date | Oct 28, 2003 |
| Priority date | — |
| Expiry date | Oct 31, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for reading flash memory cell with SONOS structure is disclosed. The flash memory cell with SONOS structure includes a P-well in a substrate, a tunneling oxide layer on the substrate, a charge trapping layer on the tunneling oxide layer, a dielectric layer on the charge trapping layer, a gate conductive layer on the dielectric layer, and source and drain regions in the substrate adjacent to the gate conductive layer. The flash memory cell with SONOS structure is read by applying a positive voltage to the drain region, floating the source region, grounding the P-well to generate gate induced drain leakage current and determining the gate induced drain leakage from the drain region to read the data in the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.