Decoder circuit in a semiconductor memory device
US6639867B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 26, 2002 |
| Grant date | Oct 28, 2003 |
| Priority date | — |
| Expiry date | Mar 26, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A decoder circuit in a semiconductor memory device for improving the productivity of a semiconductor memory device by reducing the area occupied by a decoder. In order to accomplish this, a decoder circuit in a semiconductor memory device comprises a decoder control unit for receiving an external clock signal and a reset signal to generate a clear signal, an internal reset signal, a plurality of driver enable signals and a plurality of shift register enable signals; and a plurality of decoders for decoding the clear signal, the internal reset signal, the plurality of driver enable signals and the plurality of shift register enable signals to generate a plurality of wordline-driving signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.