Clock-synchronous semiconductor memory device
US6639869B2 · kind B2 · utility
10Cited by
27References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2002 |
| Grant date | Oct 28, 2003 |
| Priority date | — |
| Expiry date | Dec 6, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device comprises a memory cell array, a counting circuit, a control circuit, a specification circuit, a selection circuit and a data I/O circuit. The selection circuit effects switching between a normal mode and a synchronous mode in a mode setting cycle. In the normal mode, setting of addresses is performed irrespective of a clock signal. In the synchronous mode, an edge of the clock signal determines the timing of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.