Apparatus and method of utilizing Alias Hit signals to detect errors within the real address tag arrays

US6640293B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Jose Angel Paredes · Austin, US
• Bruce Joseph Ronchetti · Austin, US
• Binta M. Patel · Austin, US
• George McNeil Lattimore · Austin, US

Key dates

• Filing date: Jul 24, 2000
• Grant date: Oct 28, 2003
• Expiry date: Oct 1, 2021

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F12/1063
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A data processing system including a processor having a load/store unit and method for utilizing alias hit signals to detect errors within the read address tag arrays.Within a load store unit, implemented within a processor, a real address tag array is utilized to indicate when effective address aliasing occurs in a primary cache array. If aliasing occurs, Alias Hit signals are then used to clear any aliased entries. These Alias Hit signals can also be utilized to determine if there has been some type of failure within the real address tag array.