System and method for setup and hold characterization in integrated circuit cells
US6640330B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 24, 2001 |
| Grant date | Oct 28, 2003 |
| Priority date | — |
| Expiry date | Feb 4, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An invention is disclosed for setup and hold time characterization in an integrated circuit cell. A setup time is obtained for a first constraint pin. A setup time is also calculated for a test point defined in the integrated circuit cell using the setup time for the first constraint pin and a first propagation delay from the first constraint pin to the test point. A setup time for a second constraint pin is determined based on the setup time for the test point and a second propagation delay from the second constraint pin to the test point. In addition to the setup time, a hold time can be obtained for the first constraint pin, and a hold time for the test point can be calculated using the hold time for the first constraint pin and the first propagation delay. Further, a hold time for the second constraint pin can be determined based on the hold time for the test point and the second propagation delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.