Memory device structure and method of fabricating the same

US6642111B1 · kind B1 · utility

Assignee

• POWERCHIP SEMICONDUCTOR CORP. · TW

Inventors

• Hann-Jye Hsu · Zhuolan Township, TW
• Chih-Wei Hung · Baoshan, TW

Key dates

• Filing date: Jul 9, 2002
• Grant date: Nov 4, 2003
• Expiry date: Jul 9, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

A method of fabricating a memory device structure, where the method includes the steps of forming a tunnel oxide layer, a silicon nitride layer and a silicon oxide layer. A conductive layer is then formed on top of the silicon oxide. The conductive layer is then patterned to form a conductive gate layer. The silicon oxide layer is patterned during the same step of patterning the conductive layer, exposing the silicon nitride layer. Following that, a blanket dielectric layer is then formed on the substrate. This blanket dielectric layer is patterned with one etch step to form a spacer wall at the sides of the conductive gate layer.