Double-gate FET with planarized surfaces and self-aligned silicides
US6642115B1 · kind B1 · utility
52Cited by
13References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2000 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Oct 18, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
It is, therefore, an object of the present invention to provide a structure and method for an integrated circuit comprising a first gate, a second gate, and source and drain regions adjacent the first and second gates, wherein the structure has a planar upper structure and the first gate, source and drain regions are silicided in a single self-aligned process (salicide).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.