Guy M. Cohen
320Patents
30h-index
202Co-inventors
93Inventor score
Filing activity: Mar 19, 1999 → Aug 19, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6992932B2 | Method circuit and system for read error detection in a non-volatile memory array | Physics | 317 | Expired |
| US8927968B2 | Accurate control of distance between suspended semiconductor nanowires and substrate surface | Emerging Cross-Sectional Technologies | 281 | Active |
| US7446025B2 | Method of forming vertical FET with nanowire channels and a silicided bottom contact | Emerging Cross-Sectional Technologies | 138 | Active |
| US7795677B2 | Nanowire field-effect transistors | Emerging Cross-Sectional Technologies | 138 | Active |
| US6963505B2 | Method circuit and system for determining a reference voltage | Physics | 123 | Expired |
| US6365465B1 | Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques | Electricity | 94 | Expired |
| US7230286B2 | Vertical FET with nanowire channels and a silicided bottom contact | Emerging Cross-Sectional Technologies | 87 | Expired |
| US7125785B2 | Mixed orientation and mixed material semiconductor-on-insulator wafer | Electricity | 85 | Expired |
| US6667528B2 | Semiconductor-on-insulator lateral p-i-n photodetector with a reflecting mirror and backside contact and method for forming the same | Emerging Cross-Sectional Technologies | 69 | Expired |
| US6645861B2 | Self-aligned silicide process for silicon sidewall source and drain contacts | Electricity | 61 | Expired |
| US7033927B2 | Apparatus and method for thermal isolation, circuit cooling and electromagnetic shielding of a wafer | Electricity | 60 | Expired |
| US6642115B1 | Double-gate FET with planarized surfaces and self-aligned silicides | Electricity | 52 | Expired |
| US7136304B2 | Method, system and circuit for programming a non-volatile memory array | Physics | 46 | Expired |
| US6475072B1 | Method of wafer smoothing for bonding using chemo-mechanical polishing (CMP) | Electricity | 45 | Expired |
| US7534675B2 | Techniques for fabricating nanowire field-effect transistors | Emerging Cross-Sectional Technologies | 43 | Active |
| US7101762B2 | Self-aligned double gate mosfet with separate gates | Electricity | 41 | Expired |
| US10076176B2 | Vanity mirror comprising light sources and methods of manufacture thereof | Mechanical Engineering; Lighting; Heating | 41 | Active |
| US7884004B2 | Maskless process for suspending and thinning nanowires | Emerging Cross-Sectional Technologies | 40 | Active |
| US6503833B1 | Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed thereby | Electricity | 40 | Expired |
| US9586755B1 | Dual sensing receptacles | Emerging Cross-Sectional Technologies | 39 | Active |
| US6300218A | Method for patterning a buried oxide thickness for a separation by implanted oxygen (simox) process | Electricity | 38 | Expired |
| US7060585B1 | Hybrid orientation substrates by in-place bonding and amorphization/templated recrystallization | Electricity | 36 | Expired |
| US9856080B2 | Containers with multiple sensors | Emerging Cross-Sectional Technologies | 36 | Active |
| US8399314B2 | p-FET with a strained nanowire channel and embedded SiGe source and drain stressors | Electricity | 35 | Active |
| US8384065B2 | Gate-all-around nanowire field effect transistors | Electricity | 32 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.