Integrated circuits having adjacent P-type doped regions having shallow trench isolation structures without liner layers therein therebetween and methods of forming same
US6642125B2 · kind B2 · utility
16Cited by
2References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2001 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Dec 7, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit substrate includes first and second adjacent p-type doped regions spaced-apart from one another. A trench in the integrated circuit substrate is between the first and second adjacent p-type doped regions. An insulator layer in the trench has a side wall, wherein the side wall is free of a layer that reduces a stress between the integrated circuit substrate and the insulator layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.