Gyo-young Jin
26Patents
8h-index
36Co-inventors
71Inventor score
Filing activity: Aug 4, 1999 → Feb 7, 2013
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6683364B2 | Integrated circuit devices including an isolation region defining an active region area and methods for manufacturing the same | Electricity | 74 | Expired |
| US7223649B2 | Method of fabricating transistor of DRAM semiconductor device | Electricity | 58 | Expired |
| US7056781B2 | Method of forming fin field effect transistor | Electricity | 38 | Expired |
| US6194309A | Method for forming contact | Electricity | 29 | Expired |
| US7015106B2 | Double gate field effect transistor and method of manufacturing the same | Electricity | 20 | Expired |
| US6642125B2 | Integrated circuits having adjacent P-type doped regions having shallow trench isolation structures without liner layers therein therebetween and methods of forming same | Electricity | 16 | Expired |
| US7622778B2 | Semiconductor device having shallow trench isolation structure comprising an upper trench and a lower trench including a void | Electricity | 10 | Active |
| US8884340B2 | Semiconductor devices including dual gate electrode structures and related methods | Electricity | 9 | Active |
| US8264022B2 | Semiconductor device including contact plug and associated methods | Electricity | 8 | Active |
| US9349724B2 | Semiconductor device having capacitors | Electricity | 6 | Active |
| US7501668B2 | Semiconductor memory devices having contact pads with silicide caps thereon | Electricity | 5 | Active |
| US9276074B2 | Methods of fabricating semiconductor devices having buried channel array | Electricity | 4 | Active |
| US7288823B2 | Double gate field effect transistor and method of manufacturing the same | Electricity | 4 | Expired |
| US8362536B2 | Semiconductor device having vertical channel transistor and methods of fabricating the same | Electricity | 4 | Active |
| US7265011B2 | Method of manufacturing a transistor | Electricity | 4 | Expired |
| US7307008B2 | Methods of forming integrated circuit devices including a multi-layer poly film cell pad contact hole | Electricity | 3 | Expired |
| US8492832B2 | Semiconductor device | Electricity | 3 | Active |
| US8785998B2 | Semiconductor device having vertical channel transistor and methods of fabricating the same | Electricity | 3 | Active |
| US6974752B2 | Methods of fabricating integrated circuit devices having uniform silicide junctions | Electricity | 3 | Expired |
| US6875649B2 | Methods for manufacturing integrated circuit devices including an isolation region defining an active region area | Electricity | 3 | Expired |
| US7144798B2 | Semiconductor memory devices having extending contact pads and related methods | Electricity | 2 | Expired |
| US7737512B2 | Integrated circuit devices having uniform silicide junctions | Electricity | 1 | Active |
| US7329927B2 | Integrated circuit devices having uniform silicide junctions | Electricity | 0 | Expired |
| US7297596B2 | Method of manufacturing a semiconductor device having a switching function | Electricity | 0 | Active |
| US7833864B2 | Method of doping polysilicon layer that utilizes gate insulation layer to prevent diffusion of ion implanted impurities into underlying semiconductor substrate | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.