Method of making a low fabrication cost, high performance, high reliability chip scale package
US6642136B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2001 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Sep 17, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/054
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A new method and chip scale package is provided. A point of electrical contact over a substrate is exposed through an opening created through overlying layers of passivation and polymer or elastomer, deposited over the substrate. A barrier/seed layer is deposited. A first photoresist mask exposes the barrier/seed layer where this layer overlies and is adjacent to the contact pad. The exposed surface of the barrier/seed layer is electroplated. The first photoresist mask is removed, a second photoresist mask is created to define the solder bump exposing a surface area of the barrier/seed layer not overlying the contact pad. The solder bump is created, the second photoresist mask is removed. The exposed barrier/seed layer is etched in accordance with the electroplating, reflow of the solder bump is optionally performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.