Ming-Ta Lei
58Patents
11h-index
60Co-inventors
81Inventor score
Filing activity: Feb 2, 1998 → Aug 4, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6649509B1 | Post passivation metal scheme for high-performance integrated circuit devices | Electricity | 107 | Expired |
| US7176137B2 | Method for multiple spacer width control | Electricity | 101 | Expired |
| US6605528B1 | Post passivation metal scheme for high-performance integrated circuit devices | Electricity | 88 | Expired |
| US7902679B2 | Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump | Electricity | 81 | Active |
| US6917119B2 | Low fabrication cost, high performance, high reliability chip scale package | Electricity | 81 | Expired |
| US6642136B1 | Method of making a low fabrication cost, high performance, high reliability chip scale package | Electricity | 76 | Expired |
| US6815324B2 | Reliable metal bumps on top of I/O pads after removal of test probe marks | Electricity | 45 | Expired |
| US6335249B1 | Salicide field effect transistors with improved borderless contact structures and a method of fabrication | Electricity | 22 | Expired |
| US6710413B2 | Salicide field effect transistors with improved borderless contact structures and a method of fabrication | Electricity | 18 | Expired |
| US7465653B2 | Reliable metal bumps on top of I/O pads after removal of test probe marks | Electricity | 14 | Expired |
| US7253531B1 | Semiconductor bonding pad structure | Electricity | 12 | Expired |
| US6943077B2 | Selective spacer layer deposition method for forming spacers with different widths | Electricity | 11 | Expired |
| US7355288B2 | Low fabrication cost, high performance, high reliability chip scale package | Electricity | 10 | Expired |
| US7338890B2 | Low fabrication cost, high performance, high reliability chip scale package | Electricity | 10 | Expired |
| US6746900B1 | Method for forming a semiconductor device having high-K gate dielectric material | Electricity | 9 | Expired |
| US8158508B2 | Structure and manufacturing method of a chip scale package | Electricity | 8 | Active |
| US9369175B2 | Low fabrication cost, high performance, high reliability chip scale package | Electricity | 7 | Active |
| US9653594B2 | Semiconductor device and method for forming the same | Electricity | 6 | Active |
| US7271103B2 | Surface treated low-k dielectric as diffusion barrier for copper metallization | Electricity | 5 | Expired |
| US8178967B2 | Low fabrication cost, high performance, high reliability chip scale package | Electricity | 3 | Active |
| US8901733B2 | Reliable metal bumps on top of I/O pads after removal of test probe marks | Electricity | 3 | Active |
| US6033999A | Method of solving contact oblique problems of an ILD layer using a rapid thermal anneal | Electricity | 2 | Expired |
| US10658482B2 | Plate design to decrease noise in semiconductor devices | Electricity | 2 | Active |
| US8481418B2 | Low fabrication cost, high performance, high reliability chip scale package | Electricity | 2 | Active |
| US9529956B2 | Active region design layout | Electricity | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.