High density ROM architecture
US6642587B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2002 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Aug 7, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ROM array which provides for reduced size and power consumption. The bit cell of the ROM provides that a first type of information is stored in the bit cell when a transistor is disposed between a bit line and a word line, and a second type of information is stored in the cell when no transistor is disposed between the bit line and the word line. In the bit cell a contact between a bit line and a region where a transistor drain can be formed in a substrate is provided in those instances when a transistor is formed between the bit line and a word line. In those instances when a bit cell provides no transistors between the word line and the bit line, no contact is provided between the bit line and the region where a transistor drain can be formed. Further, where a bit cell does not provide a transistor between the bit line and the word line a bit cell region in the substrate can consist substantially of an isolating dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.