Frequency multiplier design
US6642756B1 · kind B1 · utility
2Cited by
2References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2002 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Jul 25, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/00006
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency multiplier design that uses a flip-flop to output (1) a first edge on an output clock signal upon receipt of a first transition of an input clock signal and (2) a second edge on the output clock signal before receipt of a second transition of the input clock signal is provided. The frequency multiplier design uses circuitry dependent on the output clock signal to reset the flip-flop after some delay but before the second transition of the input clock signal, wherein the resetting of the flip-flop causes the flip-flop to output the second edge on the output clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.