Variable level memory
US6643169B2 · kind B2 · utility
82Cited by
6References
56Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2001 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Sep 18, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There exists a tradeoff between the fidelity of data storage and the number of bits stored in a memory cell. The number of bits may be increased per cell when fidelity is less important. The number of bits per cell may be decreased when fidelity is more important. A memory, in some embodiments, may change between storage modes on a cell by cell basis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.